The present invention relates to an etching method that may be adopted to achieve a dual damascene structure.
As higher integration in semiconductor integrated circuits is pursued with increasing vigor, rapid progress has been made in the field of the technology for manufacturing multilayered semiconductor devices in recent years. It is necessary to form both trench wiring to connect elements arranged along the horizontal direction and via hole wiring to connect elements arranged along the vertical direction when manufacturing a semiconductor device with a multilayer structure. In recent years, copper, due to its low resistance and outstanding antielectro-migration characteristics, is typically used as the wiring material. An organic low-k (Low-dielectric-constant) material such as SiLK™ (product of Dow Chemical, U.S.), which assures a low dielectric constant, is used as a layer insulating film material with a low dielectric constant of 4 or lower relative to the dielectric constant of quartz. Alternatively, an inorganic low-k material, such as fluorine-added silicon oxide (hereafter referred to as an FSG film) with a low dielectric constant, is used for the layer insulating material.
It is to be noted that a wiring pattern is formed with copper, with which a compound with a high vapor pressure cannot easily be formed, by adopting a so-called damascene structure with an embedded wiring achieved through metal CMP technology. In addition, semiconductor elements with a so-called dual damascene structure achieved by simultaneously forming trench wiring for connecting the individual elements arranged along the horizontal direction and via wiring for connecting the elements arranged along the vertical direction have become increasingly common recently. When creating such a dual damascene structure, the insulating layer is etched by using a hard mask formed through patterning to form the trenches and the vias.
FIGS. 7 and 8 present an example of a process through which a dual damascene structure is formed in the related art. As shown and FIG. 7A, an FSG layer 4 constituted of an inorganic low-k film is formed as a layer insulating film on top of an SiN layer 2 provided as a protective film. Over the FSG layer 4, a SiLK™ layer 6 constituted of an organic low-k film is formed and over the SiLK™ layer 6, an SiO2 layer 8 constituting a first hard mask and a silicon oxide nitride film (hereafter referred to as an SiON film) layer 10 constituting a second hard mask are formed as hard mask layers to be used to form trenches and vias. Over the hard mask layers, a photoresist (PR) layer 12 having a pattern to be used for trench formation is formed.
First, as shown in FIG. 7B, the SiON layer 10 constituting the second hard mask is etched through a specific lithography process by using the photoresist (PR) layer 12 for trench formation and thus, a trench pattern is formed. Then, as shown in FIG. 7C, a photoresist (PR) layer 14 for via formation is formed.
Next, as shown in the FIG. 7D, the SiO2 layer 8 constituting the first hard mask is etched through a specific lithography process by using the photoresist (PR) layer 14 for via formation and thus, a via pattern is formed.
Then, using the hard mask for via formation formed in the preceding step, the SiLK™ layer 6 constituted of an organic low-k film is etched to form a via and the photoresist (PR) layer 14 is removed through ashing as shown in FIG. 7E.
Next, as shown in FIG. 7F, a trench pattern is formed at an Sio2 layer 8 constituting the first hard mask by using the trench pattern at the SiON layer 10 formed as the second hard mask and also, vias are formed at the FSG layer 4 by using the via formed at the SiLK™ layer 6 a via pattern.
Next, as shown in FIG. 8A, the trench pattern at the SiO2 layer 8 constituting the first hard mask and the SiON layer 10 constituting the second hard mask is used to form a trench pattern at the SiLK™ layer 6.
Next, as shown in FIG. 8B, the SiN layer 2 is etched by using the via pattern at the FSG layer 4 to form through via holes. Thus, a dual damascene structure is completed by forming the trenches and the vias simultaneously. Then, the wiring process is completed by embedding Cu or a metal containing Cu (not shown) into the trenches and the vias.
However, during a step in which a hard mask becomes exposed in the process described above, shoulder sag, whereby the shoulders of the hard mask are ground and the shoulder edges become tapered, tends to occur readily. For instance, during the step shown in FIG. 7F, shoulder sag occurs as shown in FIG. 9 at the SiO2 layer 8 constituting the first hard mask and the SiON layer 10 constituting the second hard mask which have become exposed due to over-etching after removing the photoresist (PR) layer 14.
The shoulder sag that occurs at the SiON layer 10 constituting the second hard mask, in particular, cannot be corrected through subsequent steps and rather, the shoulder tends to become further ground through etching in the subsequent steps. The shoulder sag occurring at the hard mask induces over-polishing (dishing) over densely patterned areas during a post-processing step such as a CMP step, which, in turn, may lead to shorting of the wiring.
An object of the present invention, which has been completed by addressing the problem discussed above, is to provide an etching method for achieving a dual damascene structure, through which the extent of shoulder sag at a hard mask can be minimized.